Simulation models are commonly used to evaluate the
performance of parallel architectures and predict the
impact of algorithmic and architectural innovations on the
performance of parallel applications. To reduce simulation
times, most simulators
typically use direct execution to simulate the local
portions of their code and use models only for the communication
and input/output events. Even with direct execution,
sequential simulation of large parallel programs can be
very time consuming [BDCW91,DGH91,CDJ
91].
This has lead to a variety of
attempts to use parallel execution to reduce simulation
times for models that simulate parallel
programs [LW96,RHL
93,DHN94].
Most of the existing parallel program simulators are used
to evaluate the performance of the memory hierarchy,
interconnection network, or processor architecture.
To the best of our knowledge, none of the existing parallel
simulators have been used to evaluate parallel I/O systems.
Specific contributions of this paper include:
95]
The rest of the paper is organized as follows: the next section presents an overview of the subset of MPI-IO and the parallel file system that is simulated. Section 3 describes the architecture of the simulator and provides a brief desription of each of the primary components in the simulator. Section 4 describes the benchmarks and the experimental results.